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Multi-lag cross-correlations (X-Corr) are essential building blocks in radar and communication for range/velocity detection and synchronization. Performing X-corrs necessitates efficient delay and correlation blocks. Traditionally, high bandwidth X-corr is performed using high-speed ADCs followed by digital multiply-and-accumulates (MACs). However, 5–20 TOPS/W X-Corr efficiencies lead to 0.1-1W per cross-correlator, limiting deployability in power-constrained applications. Alternatively, to realize X-corr using prior single-lag analog correlators, wideband analog delays (>10ns delays with 4GHz BW) should be integrated on chip to enable multiple lags. Furthermore, replicating N analog correlators, leads to an impractical chip area. Therefore, practical analog X-Corr requires: (i) high input bandwidths, (ii) long correlation length, N for high signal processing gain (SPG=10log10(N)), (iii) high compute-efficiency (>100 TOPS/W) with compute accuracy compared to digital MACs (>7-bit), (iv) single-shot readout across all N X-corr lags in a compact area. In this work, we leverage a sampling-based approach to create large analog delays and area/power-efficient four-transistor analog compute cell to present a margin-propagation (MP) based fully-analog X-Corr compute engine in 22nm SOI-CMOS achieving: (i) 1-4GS/s input, (ii) single-shot 256-length X-Corrs across all 256 lags resulting in a 256x256 X-correlator, 8.2-8.5 bit compute accuracy or hardware dynamic range (HDR) of 51-53dB, (iii) high compute efficiency of 996–1060 TOPS/W (6.6x better than SoA), (iv) high compute density of 1.3 TOPS/mm2 (7x better than SoA). We also demonstrate an X-band code-domain radar with a range resolution of 15cm across 256 range bins, supporting up to 1024 chirp averages with a 115Hz refresh rate.